1. Field of the Invention
The present invention relates to a semiconductor memory device and, more specifically, to an improvement in an interconnecting structure of a semiconductor memory device having stacked capacitor in each memory cell.
2. Description of the Background Art
In most types of dynamic semiconductor memory devices (hereinafter referred to as DRAMs), each memory cell comprises one transfer gate transistor and one capacitor. Devices of such types are suitable for higher degree of integration, since the number of elements constituting a memory cell is small. DRAMs having stacked capacitors in which capacitors are stacked in three dimensions have been proposed so as to further improve the degree of integration. One example of such DRAMs is disclosed in Japanese Patent Publication No. 2784/1985. The structure of the memory cell in the stacked type DRAM will be described with reference to FIGS. 4 and 5.
FIG. 4 is a plan view of the memory cell and FIG. 5 shows a cross sectional structure thereof viewed from the direction along the line V--V of FIG. 4.
Referring to these figures, a plurality of word lines 1a, 1b, 1c and 1d are formed in a row direction and a plurality of bit lines 2a and 2b are formed in the column direction of a memory cell array in the DRAM. The bit lines 2a and 2b which are adjacent to each other constitute a pair of bit lines. The bit line pair is connected to a sense amplifier. One transfer gate transistor 3 and one capacitor 4 are formed near each of the intersections between the word lines and the bit lines. The transfer gate transistor 3 comprises a gate electrode 1c (formed of a portion of the word line 1c) formed on a surface of a semiconductor substrate 5 with a gate oxide film 6 interposed therebetween. Portions around the gate electrode 1c are covered with an insulating film 7. Impurity regions 8a and 8b are formed on the surface region of the semiconductor substrate 5 in self-alignment with the gate electrode 1c. The impurity regions 8a and 8b will be the source/drain regions of the transistor. A lower electrode 9 of the capacitor 4 is formed on the surface of the impurity region 8b. The lower electrode 9 extends from above the gate electrode 1c toward a portion above the word line 1b running on the field oxide film 18, with insulating films 7 and 7a interposed respectively therebetween. A dielectric film 10 having a two-layer structure including a silicon nitride film and an oxide film is formed on the surface of the lower electrode 9. An upper electrode 11 of the capacitor 4 is formed thereon. The lower electrode 9, the dielectric film 10 and the upper electrode 11 constitute a capacitor 4. An interlayer insulating film 12 formed of a silicon oxide film or the like is formed on the capacitor 4. The bit line 2b formed of aluminum (Al) is deposited by sputtering on the surface of the interlayer insulating film 12. The bit line 2b is connected to one impurity region 8b of the transfer gate transistor 3 through a contact hole 13.
As described above, in the stacked type DRAM, the capacitor 4 has a structure stacked in three dimension, and accordingly the device is thick in the direction of stacking compared with, for example, a planar type DRAM. For example, the bit line 2b is formed in a region 3000 to 6000 .ANG. higher from the surface of the semiconductor substrate. Therefore, interconnections such as the bit line 2b, which are formed at relatively high portions from the surface of the semiconductor substrate, are generally formed on regions having various ups and downs. Therefore, patterning of the interconnecting layer is difficult, as will be described with reference to FIG. 6. FIG. 6 is a schematic cross sectional view showing the step of patterning of the bit line 2b formed on the surface of the interlayer insulating film 12, in which the longitudinal direction of the bit line 2b corresponds to the direction vertical to the sheet. A contact hole 13 is formed in the interlayer insulating film 12. An aluminum layer 2b is deposited on the surface thereof by sputtering. A resist 14 is applied on the surface thereof. A mask 15 for forming patterns aligned with the semiconductor substrate is arranged above the resist 14 with a space provided therebetween. The mask 15 for patterning has a region 17 for intercepting exposure light. Portions of the resist region 14b and the aluminum layer 2b which are covered with the light intercepting region 17 are the regions constituting the desired bit line 2b. The exposing light 16 emitted from an exposing apparatus reaches the resist 14 through the mask 15 for patterning. The prescribed regions 14a of the resist 14 is exposed by the light. However, the exposing light passed through the resist 14 is reflected by the aluminum layer 2b as it highly reflects the exposing light 16. In addition, there are many ups and downs in the bit line 2b formed on the upper layer, as it is influenced by the shapes of the capacitor 4 and the transistor 3 formed therebelow. Consequently, part of the exposing light 16 is irregularly reflected to enter and expose a region 14b of the resist 14 which should not be exposed. As a result, the pattern formed on the resist 14 becomes narrower than the prescribed pattern widths. When the bit line 2b is etched by using said resist pattern as a mask, the resulting bit line 2b may be thin and may possibly be cut in some cases.
FIG. 7 is a schematic plan view of the bit line 2b whose width is narrower than the prescribed width. Such a bit line 2b narrower than the prescribed width may possibly be cut by electromigration, and the wiring resistance may possibly be increased.